A method for producing isolated junctions in a metal-oxide-semiconductor (MOS) transistor described. More specifically, the present invention describes a method for isolating the source and the drain of the transistor by forming an insulation layer adjacent to the source and an insulation layer adjacent to the drain.
A conventional metal-oxide-semiconductor (MOS) transistor generally includes a semi-conductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack comprised of a conductive material (a gate conductor), an oxide layer (a gate oxide), and sidewall spacers, is typically located above the channel. The gate oxide is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor.
A problem that arises in MOS transistors involves an internal current leakage between the source and drain. Internal current leakage is one of the limiting factors in the scaling of MOS transistors to smaller dimensions. As the source and drain physically approach one another, the drain potential may couple into the channel, causing Drain-Induced Barrier Lowering (DIBL). This DIBL results in a current leakage between the source and drain, and at short channel lengths can result in failure of the transistor. Also as the dopant levels in the junctions increase and the physical dimensions become smaller the p-n junction leakage increases.
Another problem that arises in MOS transistors involves an external current leakage between the source and/or drain and a neighboring transistor or other structures. When transistors are densely packed, current leakage across neighboring transistors and/or other structures can decrease the efficiency of the transistor and/or other structures.
A third problem that arises in MOS transistors involves parasitic capacitance. Parasitic capacitance, associated with all p-n junctions, tends to slow the maximum switching speed of the transistor.
A prior art technique to control the external current leakage and to reduce capacitance associated with junctions is to use a silicon-on-insulator (SOI) structure. However, the SOI structure has several undesirable consequences. Using the SOI structure, the source, drain and channel are formed on the insulator. Although the insulator isolates the source and drain from other devices, it also isolates an area under the channel, a sub-channel region. As the transistor operates, charges can accumulate in the sub-channel region. Since the sub-channel is isolated by the insulator a xe2x80x9cfloating bodyxe2x80x9d, which allows the channel potential to vary during device operation, is produced. In addition, in many cases the insulator is a poor thermal conductor. As a result, as the transistor operates, the insulator absorbs and traps in a large amount of heat energy, raising the temperature of the transistor.
The present invention addresses some of the shortcomings noted above.